Data processing systems
US4041464A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 1, 1975 |
| Grant date | Aug 9, 1977 |
| Priority date | — |
| Expiry date | Jul 1, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q3/54591
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Several forms of scanner are known: exception reporting, 3-cycle scanning with block exception reporting and response-mode reporting. Additionally positive-edge reporting is now required. The present invention enables the achievement of all these requirements within a rationalized scheme involving a considerably extended field size, and therefore, using a "last-look" 256 or 512 bit shift-register. This is employed in conjunction with a pre-programmed read-only memory, which stores for each different field-type served by the scanner a program relevant to that field. Each program address is formed by injecting the state of the scanned point as a least significant bit carry into an adder fed with (i) the N-1 most significant bits of the previous address in a sequence control register and (ii) an address increment value read from the location previously addressed while the current state of the last-look shift register is used as the least significant bit. Each program location stores an address increment value and last-look shift register update bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.