Delay circuitry
US4041533A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 1975 |
| Grant date | Aug 9, 1977 |
| Priority date | — |
| Expiry date | Sep 19, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/14
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A delay circuitry for producing a delayed signal the gain of which is stable irrespective of drift and fluctuation of the delay time of a delay line employed therein, which drift and fluctuation are caused by the changes in the conditions around the delay line. In this circuitry, a carrier signal is modulated with an input signal and the modulated carrier signal is then delayed in the delay line, the delay time of which is unstable due to the conditions around the delay line. The modulated and delayed carrier signal is detected by a synchronous detector with a reference signal, the phase of which is adjusted so that it is always in phase with the modulated and delayed carrier signal to produce the delayed signal which is stable irrespective of the drift and the fluctuation of the delay time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.