Digital encoder/decoder
US4042921A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 17, 1974 |
| Grant date | Aug 16, 1977 |
| Priority date | — |
| Expiry date | Sep 17, 1994 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/024
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An average peak slope companded delta codec for converting an analog signal to a corresponding digital signal and vice versa includes a comparator which receives an analog signal and a variable reconstruction signal and converts the analog signal into a digital data bit stream. A detector is provided for detecting the presence of preselected sequences of bits in the digital bit stream. An attack/decay signal is generated wherein the signal increases upon the occurrence of the preselected sequence and decreases upon the non-occurrence of the preselected sequence with the ratio of the increase to decrease of the attack/decay signal being in the range of 30:1 to 500:1. A converter means receives the attack/decay signal and generates a compand signal which is substantially an anti-logarithmic function of the attack/decay signal wherein the rate of increase of the compand signal is in the range of 0.75 dB/bit period to 3.0 dB/bit period. The compand signal is accumulated to form the variable reconstruction signal which is coupled to the input of the comparator. A means is provided for inverting the polarity of the compand signal when the reconstruction signal exceeds the analog input si…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.