N-channel MOS transistor
US4042945A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 1975 |
| Grant date | Aug 16, 1977 |
| Priority date | — |
| Expiry date | Jul 14, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
Abstract
An N-channel MOS transistor wherein two layers of different dielectric materials (e.g., silicon dioxide and silicon nitride) are used in conjunction with a P-doped silicon gate to permit the use of a higher resistivity P-type substrate. This enables a higher junction breakdown voltage and a higher threshold voltage without a reverse bias on the substrate due to an increase in the work function difference between the gate and substrate. Because of the lower concentration (i.e., higher resistivity) of the substrate, high frequency response is increased due to lower drain-source capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.