Microprogram data processing technique and apparatus
US4042972A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 1974 |
| Grant date | Aug 16, 1977 |
| Priority date | — |
| Expiry date | Sep 25, 1994 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/265
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprogrammed processor in which control signals for data paths, the ALU function, the shifter and all other control signals are derived from the current microprogram control word which is normally periodically clocked into a ROM buffer. The processor provides for microbranching capability with and/or without a test, testing capabilities including direct addressing with simultaneous temporary address storage capability for future recall, and selective testing of computer instruction bits for decoding to address the next micro-instruction. Additional capabilities provide for flexible access to the micro-code instruction control store through a ROM address multiplexer which allows for selection of at least one of four possible micro-instruction addresses determined by micro-code control decode logic. The above functions are accomplished with a fifty-six bit micro-instruction format implemented with a sixteen bit word length, which allows for a flexible instruction set for a microprogrammed processor enabling a system to be designed to span the range from a minicomputer to a large processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.