Power strobing to achieve a tri state
US4044330A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 1976 |
| Grant date | Aug 23, 1977 |
| Priority date | — |
| Expiry date | Mar 30, 1996 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and a method for coupling and uncoupling data-read lines of a memory array to a data bus. The data read-out lines of a memory array which is comprised of any combination of latched or non-latched tri-state memories are coupled to the data bus utilizing a conventional TTL circuit in combination with a power driver to simulate a tri-state buffer circuit. When the power driver removes power from the TTL circuit, a tri-state circuit is simulated; whereas when the power driver applies power to the TTL circuit, it operates in its normal mode and a normal impedance is presented between the data bus and the data-out lines of the memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.