Negative R-S triggered latch
US4045693A · kind A · utility
6Cited by
6References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 8, 1976 |
| Grant date | Aug 30, 1977 |
| Priority date | — |
| Expiry date | Jul 8, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/037
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A negative, edge-triggered R-S latch, which provides predetermined output states for any and all R-S inputs, may be obtained by using an AND-OR-Invert (A-O-I) circuit in conjunction with a "D"-type flip-flop. The reset input and the Q-output of the flip-flop provide the inputs to one AND-gate of the A-O-I circuit. The set input and Q-output of the flip-flop provide the inputs to the other AND-gate. The output of the A-O-I provides the clock input to the flip-flop. The Q-output is also connected to the D-input of the flip-flop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.