Sense amplifier for static memory device
US4045785A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 5, 1975 |
| Grant date | Aug 30, 1977 |
| Priority date | — |
| Expiry date | Nov 5, 1995 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a metal oxide silicon memory device having an array of static memory cells, a sense amplifier for detecting signals produced by the cells connected between complementary bit lines. The amplifier includes a translator section that shifts the normally high bit and bit voltage levels to a lower voltage level at the control gates of signal output devices connected to output bus lines. Each output bus line has only a single device impedance to ground rather than the normally required stacked or series arrangement of control elements. This provides a low impedance to ground for one of the output bus lines whle the signal variation around threshold provides a relatively high impedance to ground on the other bus line, thereby providing fast response times.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.