Bucket-brigade delay line having reduced parasitic capacitances

US4045810A · kind A · utility

Assignee

• General Electric Company · US

Inventors

• Walter J. Butler · Scotia, US
• Mark B. Barron · Los Angeles, US
• Bruno F. Kurz, deceased · Schenectady, US
• by Elizabeth Kurz-Beerli, executrix, also known as Elisabeth H. Kurz · Schenectady, US

Key dates

• Filing date: Jul 30, 1976
• Grant date: Aug 30, 1977
• Expiry date: Jul 30, 1996

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/895
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An MOS bucket brigade delay line having reduced parasitic capacitances include a first set of diffused drain source regions in a semiconductor substrate, a thin gate oxide layer overlying said diffused regions, a plurality of gate electrodes having first and second edges, the first edge of each electrode substantially overlapping one of said diffused regions, each of these elements formed in conventional manner. A second set of diffused drain-source regions extends the first set of regions by an amount limited by the second edge of the gate electrodes. The second set of drain source regions is formed by utilizing the gate electrodes as a diffusion mask.