Method of electrically isolating individual semiconductor circuits in a wafer
US4046605A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 1975 |
| Grant date | Sep 6, 1977 |
| Priority date | — |
| Expiry date | Jul 31, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/641
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A monolithic integrated circuit includes a vertical transistor having a low collector resistance with high current handling ability. The integrated circuit comprises a P type epitaxial layer grown on an N type substrate with both deep and shallow N type diffusions made into the P type layer. In the high current vertical transistor region with the deep N type diffusion, the deep diffusion penetrates the P layer to the N type substrate, whereas in the other transistor the shallow diffusion does not penetrate to the substrate. An N epitaxial layer is grown on the P type layer and thereafter normal processing techniques are used to form the base and emitter regions for the devices including the high current transistor which has its collector electrically coupled to the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.