Common bus parallel speed regulator system
US4047080A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 12, 1976 |
| Grant date | Sep 6, 1977 |
| Priority date | — |
| Expiry date | May 12, 1996 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S388/903
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
This disclosure relates to a parallel speed regulator system for a plurality of d.c. motors operated on a common bus having a single armature electrical supply. The speed control, current limiting, and field current controllers for each motor are arranged in parallel and connected to a resistor-diode switching network to provide a switching order of priority: (1) maximum and minimum field current controllers (2) armature current limit controllers and (3) speed controller. This parallel speed regulator system provides all the inherent advantages of the multiloop controller arrangement together with automatic adjustments which are a function of the instantaneous motor operating point, so that the dynamic response of the motor remains the same regardless of perturbations in the operating points.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.