Fault-tolerant cell addressable array
US4047163A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 1975 |
| Grant date | Sep 6, 1977 |
| Priority date | — |
| Expiry date | Jul 3, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1778
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A small programmable memory means such as an electrically programmable logic array is incorporated on the chip of a conventional bit addressable random access memory or other cell addressable array circuit. The array has one or more superfluous rows and/or columns of cells held in reserve. Processing and testing of the chip is conducted in a conventional manner. Chips with faulty cells are corrected by programming the memory means with the cell addresses of the faulty cell locations. Subsequently, the memory means will respond to any of these addresses and, through interaction with input/output logic, cause the data input and/or output to be steered to or from a reserve cell instead of the addressed faulty cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.