CPU - I/O bus interface for a data processing system
US4048673A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 1976 |
| Grant date | Sep 13, 1977 |
| Priority date | — |
| Expiry date | Feb 27, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/45
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is disclosed an input/output system, employed within a data processing system that includes a central processing unit (CPU). The CPU includes improved input/output shift register structure or interfacing means for interfacing with I/O means (bus structure). The I/O means includes improved CPU transceiver and peripheral device ransceiver apparatus. The device transceiver interfaces with an improved device controller. In the preferred embodiment of the present invention, the CPU, CPU transceiver, device transceiver, and device controller, all being constructed primarily from MOS technology, are each contained within a respective chip. Further features of the input/output system include capability for placement of multiple transceiver/controllers and their respective peripheral devices at varying distances from the CPU by virtue of novel clock and data transmission means which maintains accurate processing of data regardless of propagation delay, distortion, data skewing, etc., due to varying transmission distances and inherent limitations of MOS, bipolar, and other technology.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.