Digital frequency measuring circuitry
US4051434A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 28, 1976 |
| Grant date | Sep 27, 1977 |
| Priority date | — |
| Expiry date | May 28, 1996 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R23/09
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Circuitry for developing a binary number proportional to the frequency of an input signal includes a first and second shift register and an adder. Timing control circuitry establishes a 16 bit computation period and also develops a fixed binary number. Circuit means are provided for interconnecting the adder and the firsrt register for increasing the content of the register by the fixed binary number once each cycle of the input signal and for reducing the content of the register by a fixed proportion each of the computation periods occurring during each cycle of the input signal. The content of the first register is transferred to the second or buffer register each cycle of the input signal and display means are provided for displaying the input frequency of a function as the binary number contained in the second register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.