Binary adder
US4052604A · kind A · utility
32Cited by
6References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 19, 1976 |
| Grant date | Oct 4, 1977 |
| Priority date | — |
| Expiry date | Jan 19, 1996 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3876
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A binary adder employs separate summing and carry circuitry within each digit to optimize the speed of operation of the adder. Carry bits of less significant digits are calculated independently of corresponding sum bits, thus allowing propagation of such carry bits to more significant digits before completion of the summation of the less significant digits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.