Logic circuit of ratioless structure
US4053791A · kind A · utility
0Cited by
4References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 22, 1976 |
| Grant date | Oct 11, 1977 |
| Priority date | — |
| Expiry date | Jun 22, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/023
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A logic circuit of a ratioless structure, wherein a load MOS FET, a drive MOS FET and a pre-discharge MOS FET are connected in series in the described order, a first clock is applied to the pre-discharge MOS FET, a second clock is applied to the load MOS FET, and an input signal is applied to the drive MOS FET while an output signal is derived from the junction between the drive MOS FET and pre-discharge MOS FET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.