Low power complementary field effect transistor (CFET) logic circuit
US4053792A · kind A · utility
4Cited by
7References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 27, 1974 |
| Grant date | Oct 11, 1977 |
| Priority date | — |
| Expiry date | Jun 27, 1994 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0948
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a logic circuit implemented in complementary field effect transistor (CFET) technology for improving the transient response of CFET circuits and providing a true DOT-OR or DOT-AND logic function. The pull-up circuit includes at least one active device and is placed either in parallel with or replaces the conventional load impedance between a source of potential and the output node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.