Drain source protected MNOS transistor and method of manufacture
US4053917A · kind A · utility
4Cited by
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1Claims
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Key dates
| Filing date | Aug 16, 1976 |
| Grant date | Oct 11, 1977 |
| Priority date | — |
| Expiry date | Aug 16, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved drain source protected MNOS transistor is realized by means of a fabrication technique that permits independent control of memory and nonmemory parameters. Self alignment of memory regions during fabrication is achieved by using nitride masking for gate oxidation. Independent control of memory and nonmemory parameters derives from a device configuration in which protected regions consist exclusively of gate oxide and silicon nitride is present only in the memory regions. Transistor radiation hardening is also achieved by elimination of the nitride layer above the device's thin silicon dioxide regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.