Memory module with means for generating a control signal that inhibits a subsequent overlapped memory cycle during a reading operation portion of a reading memory cycle
US4055851A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 1976 |
| Grant date | Oct 25, 1977 |
| Priority date | — |
| Expiry date | Feb 13, 1996 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4239
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A random access memory module for connection in a memory arrangement for a digital data processing system that additionally includes a high speed associative memory unit. The associative memory unit contains a multiple location address memory and a multiple location data memory wherein there is a correspondence between each address location and a data location. Each time a central processor in the system initiates a reading operation, it issues an address to define a data location. If the associative memory unit contains that address at a location in its address memory, it performs a reading memory cycle and transfers data from the corresponding location in the data memory directly to the central processor. On the other hand, if the associative memory does not contain that address, it initiates a reading memory cycle with the random access memory module. It is possible for the associative memory unit to request successive transfers with one or more memory modules on an overlapped basis. Each memory module performs two successive operations during each transfer: namely, a reading operation and a successive writing operation. Control circuitry in the memory module generates a BUS OCC…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.