FET device with reduced gate overlap capacitance of source/drain and method of manufacture
US4056825A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 17, 1977 |
| Grant date | Nov 1, 1977 |
| Priority date | — |
| Expiry date | Feb 17, 1997 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A metal gate transistor is fabricated to have reduced gate overlap of source/drain regions and increased oxide thickness over the diffused regions whereby parasitic capacitance is reduced and switching speed is increased. The method comprises the steps of (1) selecting an appropriate insulating thickness over a semiconductor substrate, (2) forming source/drain diffused regions in the substrate through openings in the insulating layer at appropriate diffusion temperatures, (3) selecting an appropriate drivein and regrowth temperature whereby the insulating layer thickness over the diffused region is greater than that over the non-diffused region and out diffusion of the diffused regions is minimized, (4) etching the region between the source/drain to form a gate area and (5) growing a prescribed gate insulation thickness for a metal gate whereby the gate insulation overlap of the diffused region and the thickness of the gate insulation overlap of the diffused region reduce the parasitic capacitance and increase the switching speed of the resulting metal gate transistor relative to prior art transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.