Read only memory
US4057787A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 1976 |
| Grant date | Nov 8, 1977 |
| Priority date | — |
| Expiry date | Feb 13, 1996 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An FET read only memory array having bit locations arranged in rows and columns utilizes a dynamic array and static sensing. A dynamic first address selects the gate line of a selected column and a second address selects the source line or lines to select one or more bits within the selected column. The presence or absence of a gate at a selected bit location determines whether a first or second logic level is present at the sense or drain line serving the bit location. An additional column of FET bit positions each with a gate has the gate line activated toward the conclusion of the cycle to provide a path to ground for the elimination of any charge on a sense line in preparation for the next succeeding cycle. The sensed output from a selected bit location is latched until reset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.