Charge coupled device random access memory
US4060738A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 1976 |
| Grant date | Nov 29, 1977 |
| Priority date | — |
| Expiry date | Nov 8, 1996 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Semiconductor memory cells include gate conductor-insulator-semiconductor regions having storage and transfer portions in which the threshold voltage and surface potential-gate conductor voltage characteristics differ as between the storage and transfer portions. This may be achieved by employing relatively thick and relatively thin insulator areas at the storage and transfer portions, or vice versa, with a surface charge accumulation layer at the semiconductor region insulator interface. In a different form of cell structure, the insulator is a uniform thickness layer overlying the storage and transfer portions one of which includes a doped semiconductor region of the same conductivity type as, but higher dopant concentration than, the remainder of the semiconductor region. The difference in threshold voltage and surface potential characteristics is such that in response to first and second defined gate voltage levels, the potential well profile at the storage and transfer portions is changed in a manner permitting write in and read out of logic signal level related charge packets into and from the storage portion. Semiconductor memories include a matrix array of such cell structu…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.