Semiconductor memory device
US4060796A · kind A · utility
4Cited by
2References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 11, 1977 |
| Grant date | Nov 29, 1977 |
| Priority date | — |
| Expiry date | Jan 11, 1997 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/671
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device provided with one transferring electrode, one gate electrode and one diode of a charge coupled device is produced by a process with a reduced number of steps of diffusion and patterning. Both electrodes consists of doped polycrystalline silicon and both are electrically connected to a resistive layer which consists of non-doped polycrystalline silicon. A potential barrier between the region of both electrodes is removed due to the resistive layer. Resistive layer is formed by utilization of a two-stage deposition of the polycrystalline silicon layer with appropriate mashing steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.