Clock generator and delay stage
US4061933A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 1975 |
| Grant date | Dec 6, 1977 |
| Priority date | — |
| Expiry date | Dec 29, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1504
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock generator for an MOSFET integrated circuit having a plurality of cascaded delay stages is disclosed. Each delay stage includes a bootstrap inverter having first and second transistors connected in series between the drain supply voltage and a source supply voltage, thus forming a first node between the transistors. The first node is capacitively coupled to a bootstrap node which is connected to the gate of the first transistor. The bootstrap node is also coupled through the channel of a third transistor to an input. The gate of the third transistor forms a third node. Circuit means are provided for precharging the third node and then isolating the third node while an input signal is applied through the third transistor to the bootstrap node so that the third node is also bootstrapped up to permit rapid charging of the bootstrap node to the full voltage of the input signal. The second transistor is held on by a precharge signal so that the first node is held low until the bootstrap node has been charged to the input voltage. Then both the third node and the gate of the second transistor are discharged to turn the second and third transistors off, thus permitting the bootstra…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.