Circuit arrangement for the reception of data
US4061997A · kind A · utility
5Cited by
9References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 18, 1975 |
| Grant date | Dec 6, 1977 |
| Priority date | — |
| Expiry date | Nov 18, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0045
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A circuit arrangement for data transmission systems is described wherein the transmission of excessively faulty data signals is recognized and prevented, thereby stopping the transmission of senseless text. A fault discriminator emits a fault signal which is subsequently integrated. The integrated fault signal, if it exceeds a predetermined value, triggers a threshold value stage to produce a blocking signal. The blocking signal acts on the circuitry in a data sink, e.g., a teleprinter, to suppress the processing of the received data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.