Solid-state delay timed switching circuit
US4062007A · kind A · utility
9Cited by
1References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 17, 1976 |
| Grant date | Dec 6, 1977 |
| Priority date | — |
| Expiry date | Sep 17, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/292
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A solid-state delay timed switching circuit includes a delay timing means for delaying the start of an operational sequence. A function timing means is provided for timing the operational sequence, an alarm timing means for timing an audible alarm at the completion of an operational sequence, a power switching means, a power supply and a power turn-off means to de-energize the power switching means.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.