Stereo noise reduction circuit
US4063039A · kind A · utility
12Cited by
3References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 16, 1976 |
| Grant date | Dec 13, 1977 |
| Priority date | — |
| Expiry date | Jun 16, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G5/18
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A stereo noise reduction circuit is disclosed having circuitry responsive to the automatic gain control voltage generated within an FM stereo receiver for reducing the noise associated with low levels of the RF carrier. A first portion of the noise reduction circuit provides for out-of-phase noise cancellation when the automatic gain control voltage reaches a first level and a second portion provides for rolling-off the higher frequencies of the output audio signals when the automatic gain control voltage reaches a second level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.