Complementary MOS logic circuit
US4064405A · kind A · utility
28Cited by
7References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 9, 1976 |
| Grant date | Dec 20, 1977 |
| Priority date | — |
| Expiry date | Nov 9, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09482
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A complementary MOS logic circuit is disclosed. The circuit utilizes two stages with a coupling network comprising a capacitor and a diode used to couple the first stage to the second stage. This results in a circuit with the logic signal coupled to the input being inverted at the output without introducing substantial loss in signal amplitude.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.