I.I.L. with graded base inversely operated transistor

US4064526A · kind A · utility

Assignee

• Tokyo Shibaura Electric · JP

Inventors

• Yukuya Tokumaru · Yokohama, JP
• Masanori Nakai · Yokohama, JP
• Satoshi Shinozaki · Yokohama, JP
• Junichi Nakamura · Settsu, JP
• Shintaro Ito · Tokyo, JP
• Yoshio Nishi · Palo Alto, US

Key dates

• Filing date: Dec 24, 1975
• Grant date: Dec 20, 1977
• Expiry date: Dec 24, 1995

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S148/167

Abstract

An integrated injection logic semiconductor device comprises an N type semiconductor substrate, a P type semiconductor layer laminated on said semiconductor substrate, and N type first region formed in a manner penetrating through said P type semiconductor layer to reach said N type semiconductor substrate, a first P type region formed in said first N type region, a second N type regionformed in said P type semiconductor layer, and a second P type region formed between said second N type region and said N type semiconductor substrate in a manner connected directly to said N type semiconductor substrate. An integrated injection logic circuit is comprised of a lateral NPN transistor whose emitter, base and collector are constituted by said first P type region, first N type region and P type semiconductor layer, respectively, and a vertical PNP transistor whose emitter, base and collector are constituted by said N type semiconductor substrate, P type semiconductor layer plus second P type region, and second N type region, respectively.