Ion implantation process for fabricating high frequency avalanche devices
US4064620A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 1976 |
| Grant date | Dec 27, 1977 |
| Priority date | — |
| Expiry date | Jan 27, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are new high frequency ion implanted passivated semiconductor devices and a planar fabrication process therefor wherein initially an ion implantation and PN junction passivation mask is formed on one surface of a semiconductor crystal. Thereafter, one or more conductivity type determining ion species are implanted through an opening in the mask and into the semiconductor crystal to form active device regions including a PN junction, all of which are bounded by an annular, higher resistivity unimplanted region of the semiconductor crystal. The PN junction thus formed terminates beneath the implantation and passivation mask, and the semiconductor crystal is then annealed to remove ion implantation damage and to electrically activate the ion implanted regions, while simultaneously controlling the lateral movement of the PN junction beneath the passivation mask. Such annealing does not adversely affect the conductivity and passivation characteristics of either the higher resistivity annular region or the passivation mask, and the resultant device structure exhibits a small degradation in high frequency performance relative to comparable state of the art unpassivated devices. …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.