Method of fabricating high-gain transistors
US4066473A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 15, 1976 |
| Grant date | Jan 3, 1978 |
| Priority date | — |
| Expiry date | Jul 15, 1996 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/919
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating bipolar transistors with increased gain. A base region is formed adjacent the collector (or emitter) region of the transistor, and a portion of the base region is then removed by etching. The emitter (or collector) is then formed by diffusing dopant into the base region where the portion has been removed, with the base region separating the emitter and collector having reduced thickness due to the etching. Advantageously, the base region may be formed with a more heavily-doped region overlying a less heavily-doped region, with a part of the more heavily-doped region removed by etching, thereby providing a highly conductive path to the lower conductivity base region separating the emitter and collector regions. The process steps are compatible with conventional integrated-circuit fabrication processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.