Shared direct memory access controller
US4067059A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 29, 1976 |
| Grant date | Jan 3, 1978 |
| Priority date | — |
| Expiry date | Jan 29, 1996 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/285
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor system includes a microprocessor, a memory, and one or more direct memory access controllers, all connected to a common system bus which includes a system address bus and a system data bus. At least one of the direct memory access controllers is shared by a plurality of subsystem device controllers which may control peripheral devices having diverse characteristics. The microprocessor is limited in its instruction repertoire and may control peripheral devices only by means of an input and an output instruction. The shared direct memory access controller includes no circuitry which is specifically for controlling only a single type of peripheral device, the device dependent logic being located in subsystem device controllers. Data transfers may take place directly between the memory and, through the shared direct memory access controller, any selected one of the peripheral devices. In order to set up the actual data transfer, the microprocessor executes an Input instruction which addresses the status register in a selected subsystem device controller and returns this status to the microprocessor. Next, two Output instructions are executed to load a memory starting a…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.