Integrated FET circuit with input current cancellation
US4068254A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 13, 1976 |
| Grant date | Jan 10, 1978 |
| Priority date | — |
| Expiry date | Dec 13, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/45376
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit including an FET and an analog for cancelling input current that would otherwise be required to supply the FET gate leakage current. The analog establishes a leakage current the magnitude of which is a substantially fixed proportion of the FET leakage current over a given operating range, and employs proportional current mirror means referenced to the analog leakage current to supply the FET leakage current and thereby substantially cancel the input bias current. In a preferred embodiment the analog comprises a lateral PNP multi-collector transistor with one collector connected to its base to establish a reference current, another collector providing the cancellation current, and its base voltage tracking the FET gate voltage so that the two leakage currents remain substantially equal. An analog FET may also be employed to cancel gate-to-drain and gate-to-source leakages. A description of the invention as applied to an operational amplifier is given.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.