MIS logic circuit of ratioless type
US4069427A · kind A · utility
8Cited by
8References
9Claims
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Assignee
Inventor
Key dates
| Filing date | Nov 5, 1976 |
| Grant date | Jan 17, 1978 |
| Priority date | — |
| Expiry date | Nov 5, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/84
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An MIS logic circuit of a ratioless type comprising at least one logic section including one or more MIS FETs and provided with first and second electric energy suppressors which otherwise is fed back from output to input of the logic block through the gate-to-source capacitance and the gate-to-drain capacitance of the MIS FET. The first and second suppressors are connected with the drain and the source of the MIS FET respectively so that they are in series connection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.