IGFET clock generator
US4069429A · kind A · utility
16Cited by
5References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 13, 1976 |
| Grant date | Jan 17, 1978 |
| Priority date | — |
| Expiry date | Sep 13, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1515
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit having an input terminal connected to one input of a NOR gate through three cascaded IGFET inverters and connected directly to the other input of the NOR gate for producing an output pulse in response to an input signal going from a first voltage level to a second voltage level. The output pulse has a width which is a function of the time delay imparted by the high resistance device of two unbalanced IGFET inverters and the parasitic capacitors at the output of each of the unbalanced inverters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.