Read/write speed up circuit for integrated data memories
US4070656A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 1976 |
| Grant date | Jan 24, 1978 |
| Priority date | — |
| Expiry date | Nov 8, 1996 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/415
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved method of operating a monolithic memory together with novel and efficient circuitry for practicing said improved method is disclosed. In a bipolar transistor store, or monolithic memory, in accordance with the invention, a very low current (first level) flows from the load elements to the internal cell nodes in the stand-by mode. During the initial portion of a read cycle, current flows from the bit lines to the cell nodes, in addition to the stand-by current (second level). In the recovery period of the read cycle or write cycle a short pulse is added to the stand-by current (third level), thereby reducing the recovery time. The practice of the invention provides a monolithic memory having minimal power requirements and a substantially reduced cycle time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.