Four-quadrant multiplier
US4071777A · kind A · utility
19Cited by
4References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 6, 1976 |
| Grant date | Jan 31, 1978 |
| Priority date | — |
| Expiry date | Jul 6, 1996 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06G7/163
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuit employing complementary field-effect transistors operated in the triode mode. A signal representing the multiplicand is applied to the gate electrode of one transistor and a signal representing the multiplier is applied to the drain electrode of the same transistor. The complement of the multiplier signal is applied to the drain electrode of the other transistor. A current indicative of the product is available at the common connection of the source electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.