MOS input buffer with hysteresis
US4071784A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 1976 |
| Grant date | Jan 31, 1978 |
| Priority date | — |
| Expiry date | Nov 12, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/3565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An MOS input buffer circuit includes an input connected to the gate electrode of an enhancement mode input MOSFET. The drain of the input MOSFET is connected to the output of the input buffer circuit. The source of the input MOSFET is connected to the drain of a second depletion mode MOSFET having its source connected to ground and its gate connected to a V.sub.DD voltage conductor. A load circuit is coupled between the V.sub.DD voltage conductor and the output, and consists of an enhancement mode MOSFET and a depletion load MOSFET coupled in series between output and V.sub.DD voltage conductor. A third depletion mode MOSFET has its drain connected to the V.sub.DD voltage conductor, its source connected to the source of the input MOSFET, and its gate connected to the output. The positive gain (or negative slope) portion of the switching characteristic of the input buffer circuit extends substantially all the way between the high and low output levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.