MOS interchip receiver differential amplifiers employing CMOS amplifiers having parallel connected CMOS transistors as feedback shunt impedance paths
US4074151A · kind A · utility
17Cited by
9References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1976 |
| Grant date | Feb 14, 1978 |
| Priority date | — |
| Expiry date | Jun 30, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0948
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A negative shunt feedback CMOS amplifier is disclosed for connection to the output nodes of MOS interchip digital signal receiver differential amplifiers which have highly capacitive output nodes in order to bypass the large capacitance to thereby extract a high speed current signal. A first embodiment of the invention uses a resistor as the shunt feedback and a second embodiment of the invention, to which this application is directed to, uses parallel N-channel and P-channel FETs to form the shunt feedback impedance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.