Error correction of digital signals
US4074228A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 26, 1976 |
| Grant date | Feb 14, 1978 |
| Priority date | — |
| Expiry date | Oct 26, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0061
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Data bits are combined at a transmitter with parity check code bits and convolutional check code bits. On reception the parity check code bits are decoded to determine the error probability in the received signal. The convolutional check code bits are used to correct the received data according to a correction algorithm which is defined in dependence on the error probability revealed by the parity check code bits. The received data is divided into bytes and each byte is given a respective error probability rating. Circuitry including logic gates and shift registers are used to carry out the encoding, decoding and correction operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.