System for addressing and address incrementing of arithmetic unit sequence control system
US4075688A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 1976 |
| Grant date | Feb 21, 1978 |
| Priority date | — |
| Expiry date | Aug 26, 1996 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Control for overlapping instruction execution in an arithmetic unit is provided by stepping a sequence of instructions through a plurality of registers connected in cascade and separately decoding each instruction in a register for control of a corresponding stage in one or more data processing paths, each comprising stages through which data being processed is stepped, each stage corresponding to only one register of the control pipeline. The output of the decoder of each instruction register controls the required operations in the corresponding stage of the data pipeline. Automatically indexed indirect addressing is provided by use of pointers for data sources and destinations as required in the execution of every instruction in order to facilitate highly iterative and structured operations on blocks or arrays of data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.