Floating point data processor for high speech operation
US4075704A · kind A · utility
122Cited by
6References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 2, 1976 |
| Grant date | Feb 21, 1978 |
| Priority date | — |
| Expiry date | Jul 2, 1996 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3896
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital data processor includes a plurality of memory registers, a floating point adder and a floating point multiplier intercoupled by a plurality of simultaneously operable parallel buses facilitating multiple parallel operations during one clock cycle or instruction. The floating adder and multiplier each include a number of stages separated by intermediate temporary storage registers which receive the partial results of a computation for use by the next stage during the next clock period. Floating point additions, multiplications and other arithmetic and logical results are produced during each clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.