Programmed device controller
US4075707A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 21, 1976 |
| Grant date | Feb 21, 1978 |
| Priority date | — |
| Expiry date | May 21, 1996 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05B19/045
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A processing system adapted to control a sequential automated device to a state determined by the immediately preceding state. The system comprises a read only memory (ROM) (or alternatively a static RAM) having coded at each address in bit positions 2 through n the address of either the output signal to be controlled, the input signal to be sensed or the next ROM address. Bit position 0 indicates whether an output or input is to be selected and bit position 1 either determines the desired state of the input that is selected or routes the 2 through n bit position address to select the output or to set a new address for the ROM. Accordingly bits 0 and 1 from the ROM are combined with the selected input in a logical circuit comprising gates and inverters to either increment the ROM address buffer or jump to a new address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.