Self aligned gate for di-CMOS
US4075754A · kind A · utility
13Cited by
9References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 30, 1976 |
| Grant date | Feb 28, 1978 |
| Priority date | — |
| Expiry date | Mar 30, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0165
Abstract
A process for fabricating complementary metal oxide semiconductors including doping to determine threshold voltage of a first conductivity channel device with second conductivity type impurities, counter-doping to determine the threshold voltage of a second conductivity channel device with second conductivity impurities, forming gate oxide, forming metal gate, and forming source and drain regions using the metal gate as a self-aligned mask. Preferably, the doping steps are performed using ion implantation and photoresist mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.