Method for packaging hermetically sealed integrated circuit chips on lead frames
US4079511A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 30, 1976 |
| Grant date | Mar 21, 1978 |
| Priority date | — |
| Expiry date | Jul 30, 1996 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49146
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An assembly line method for fabricating hermetically sealed integrated circuit chips with externally extending terminal leads comprising the steps of securing at least one integrated circuit chip upon a spider assembly; stamping a strip of iterative lead frame assemblies from a strip of flat stock metal; encapsulating each of said lead frame assemblies with plastic in a configuration which leaves a window space in the center thereof or defined elsewhere therein, with the convergent ends of the individual conductive paths of the lead frame extending out of the plastic and into said window space, and the divergent ends of such conductive paths extending out of the plastic and away from the window space; mounting the terminal chip holding spider assembly onto the convergent ends of the conductive paths of the lead frame; inserting a first cap over the window space on one side of the encapsulating plastic; filling the window space with a sealant to completely immerse said spider bearing chip therein and having the properties of being electrically insulative and virtually completely resistant to the passage of moisture therethrough; and inserting a second cap over said window space on t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.