Virtual address translator
US4084226A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 1976 |
| Grant date | Apr 11, 1978 |
| Priority date | — |
| Expiry date | Sep 24, 1996 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A virtual address translator comprises a content addressed memory and a word addressed memory. A task name and subsegment number from a virtual address supplied by a processor are employed as a key word to search a content addressed memory and read out a subsegment descriptor if the key word is matched. The subsegment descriptor includes an absolute base address which is added to a deflection field to obtain an absolute memory address. The memory address is applied to a memory to permit transfer of a word between the processor and the memory. The processor may present any one of several task names depending upon whether the memory reference is made for an instruction or data for the processor, or for an instruction or data for an I/O connected to the processor. Bounds, residency and access privileges are checked using the subsegment descriptor. If a search of the content addressed memory reveals that the desired subsegment descriptor is not in the word addressed memory, the translator obtains the descriptor from memory and then generates the desired absolute memory address. The translator is provided with circuits generating values which indicate the efficiency of its operation. Co…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.