Apparatus for performing multiple operations in a shift register memory
US4084258A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 22, 1974 |
| Grant date | Apr 11, 1978 |
| Priority date | — |
| Expiry date | Apr 22, 1994 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F40/166
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for performing multiple operations during a memory revolution in an electronic dynamic shift register. The memory is initially arranged by the input of control codes such as record, operation, separator, and hold flags. The separator flag defines a normal section and an alternate section, and the operation and hold flags define the position of the next character to be addressed in each of the sections. The record flag is the operating point for an output operation in the normal section. When one of the sections is addressed and it does not contain the operation flag, the hold and operation flags are exchanged in order that the operation flag is in the section addressed. With the operation flag in the normal section, an input zone is defined by the separator flag in the alternate section, and a revision zone is defined from the record flag to the separator flag in the normal section. When the operation flag is in the alternate section, the input zone begins with the first dummy code following the operation flag, and the revision zone is from the separator flag to the first dummy code. An output zone is defined in the normal section by inserting a page end code and exten…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.