Phase locked loop decoder
US4085288A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 22, 1976 |
| Grant date | Apr 18, 1978 |
| Priority date | — |
| Expiry date | Oct 22, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4906
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A phase locked loop decoder for decoding digitally encoded data is disclosed in which each incoming data bit is synchronized to a clock frequency and a derived signal representative of the data cell width is varied in accordance with a derived phase error signal to compensate for bit shift and for data cell width variation which may be present in the incoming data. The phase error signal is a pulsed waveform having a leading edge synchronized with the occurrence of each data transition and a pulse width reprsentative of the phase error of the data with respect to the clock. The decoder will detect and decode data transitions having bit shifts of up to plus or minus 50 percent of the bit cell period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.