Random access memory
US4085458A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 1976 |
| Grant date | Apr 18, 1978 |
| Priority date | — |
| Expiry date | May 26, 1996 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a n-channel (or p-channel) random access memory in which a plurality of memory cells are arranged in a matrix form in a p-type (or n-type) semiconductor substrate, clamping MOSFET's are connected between word lines provided for the associated rows of memory cells of the matrix and a reference potential to which gates the source electrodes of the information storing MOSFET's of the memory cells are connected. The clamping MOSFET has a lower threshold voltage than a row selecting MOSFET connected to the word line and clamps the word line when the word line is not selected, so that a delay in the read-out operation is eliminated or suppressed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.