Digital echo suppressor
US4088851A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 1976 |
| Grant date | May 9, 1978 |
| Priority date | — |
| Expiry date | Apr 28, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B3/20
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A multi-channel digital echo suppressor wherein analog signals on a plurality of paired transmit and receive lines are sampled and digitized to form an interleaved sequence of parallel digital words. The interleaved digital words are accumulated for a predetermined period to form accumulated sample sums in sequence for each of the respective transmit and receive lines. Means are provided for segregating the receive channel accumulated samples from the transmit channel accumulated samples and bringing the samples for the respective channel pairs back into time correlation. The receive line accumulated samples are sequentially compared against a predetermined reference for producing suppression control signals which are routed to respective suppression controllers for the various channels. At the same time, the transmit line accumulated samples are compared against the time correlated receive line accumulated samples and to a predetermined reference to produce break-in control signals for each channel in sequence. The break-in control signals are monitored by a moving window scanner which selects and monitors the most recent eight break-in control signals for each channel in sequence…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.